`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   16:27:31 05/09/2012
// Design Name:   fsm_L1
// Module Name:   C:/Users/kotarf/Documents/achd-mips-soc/trunk/hdl/L1Cache/fsmtest.v
// Project Name:  L1Cache
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: fsm_L1
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module fsmtest;

	// Inputs
	reg clk;
	reg reset;
	reg [31:0] cpu_addr;
	reg cpu_rd;
	reg cpu_wr;
	reg [31:0] cpu_dout;
	reg [3:0] cpu_wmask;
	reg [31:0] l2_dout;
	reg l2_dinok;
	reg l2_dontcache;
	reg [1:0] hitindex;
	reg [1:0] dirtyindex;
	reg [31:0] mem_din_1;
	reg [31:0] mem_din_2;
	reg l1_out_rr;
	reg [1:0] l1_out_valid;
	reg [1:0] l1_out_dirty;
	reg [6:2] l1_out_index;
	reg [31:7] mem_tagin_1;
	reg [31:7] mem_tagin_2;

	// Outputs
	wire [31:0] cpu_din;
	wire cpu_dinok;
	wire [31:0] l2_addr;
	wire l2_rd;
	wire l2_wr;
	wire [31:0] l2_din;
	wire [3:0] l2_wmask;
	wire [31:0] mem_addr;
	wire [31:0] mem_dout;
	wire [31:7] l1_in_tag;
	wire [1:0] sel;
	wire l1_in_rr;
	wire l1_in_valid;
	wire l1_in_dirty;
	wire [6:2] l1_in_index;

	// Instantiate the Unit Under Test (UUT)
	fsm_L1 uut (
		.clk(clk), 
		.reset(reset), 
		.cpu_addr(cpu_addr), 
		.cpu_rd(cpu_rd), 
		.cpu_wr(cpu_wr), 
		.cpu_dout(cpu_dout), 
		.cpu_wmask(cpu_wmask), 
		.cpu_din(cpu_din), 
		.cpu_dinok(cpu_dinok), 
		.l2_dout(l2_dout), 
		.l2_dinok(l2_dinok), 
		.l2_dontcache(l2_dontcache), 
		.l2_addr(l2_addr), 
		.l2_rd(l2_rd), 
		.l2_wr(l2_wr), 
		.l2_din(l2_din), 
		.l2_wmask(l2_wmask), 
		.hitindex(hitindex), 
		.dirtyindex(dirtyindex), 
		.mem_din_1(mem_din_1), 
		.mem_din_2(mem_din_2), 
		.l1_out_rr(l1_out_rr), 
		.l1_out_valid(l1_out_valid), 
		.l1_out_dirty(l1_out_dirty), 
		.l1_out_index(l1_out_index), 
		.mem_tagin_1(mem_tagin_1), 
		.mem_tagin_2(mem_tagin_2), 
		.mem_addr(mem_addr), 
		.mem_dout(mem_dout), 
		.l1_in_tag(l1_in_tag), 
		.sel(sel), 
		.l1_in_rr(l1_in_rr), 
		.l1_in_valid(l1_in_valid), 
		.l1_in_dirty(l1_in_dirty), 
		.l1_in_index(l1_in_index)
	);
	reg ready = 0;
	initial begin
		// Initialize Inputs
		clk = 0;
		reset = 0;
		cpu_addr = 0;
		cpu_rd = 0;
		cpu_wr = 0;
		cpu_dout = 0;
		cpu_wmask = 0;
		l2_dout = 0;
		l2_dinok = 0;
		l2_dontcache = 0;
		hitindex = 0;
		dirtyindex = 0;
		mem_din_1 = 0;
		mem_din_2 = 0;
		l1_out_rr = 0;
		l1_out_valid = 0;
		l1_out_dirty = 0;
		l1_out_index = 0;
		mem_tagin_1 = 0;
		mem_tagin_2 = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		ready = 1;
	end
	
	always begin
		clk <= 0;
		#5;
		clk <= ready;
		#5;
		
		if( ready )
			$display("---CLOCK---");
	end
      
	reg[15:0] testcount = 0;
	always @(posedge clk) begin
		
		case(testcount)
			0: begin
				testcount <= 1;
				cpu_addr <= 32'hFFFFFFFF;
				cpu_rd <= 1;	
			end
			
			1: begin
				testcount <= 2;
				mem_din_1 <= 32'hBBBBBBBB;
				hitindex <= 2'b11;
			end
			
			2: begin
			end
		endcase
	end		
		
		
		
endmodule

